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MC10EP29, MC100EP29 3.3V / 5V ECL Dual Differential Data and Clock D Flip-Flop With Set and Reset
The MC10/100EP29 is a dual master-slave flip-flop. The device features fully differential Data and Clock inputs as well as outputs. The MC10/100EP29 is functionally equivalent to the MC10/100EL29. Data enters the master latch when the clock is LOW and transfers to the slave upon a positive transition on the clock input. The differential inputs have special circuitry which ensures device stability under open input conditions. When both differential inputs are left open the D input will pull down to VEE and the D input will bias around VCC/2. The outputs will go to a defined state, however the state will be random based on how the flip flop powers up. Both flip flops feature asynchronous, overriding Set and Reset inputs. Note that the Set and Reset inputs cannot both be HIGH simultaneously. The VBB pin, an internally generated voltage supply, is available to this device only. For single-ended input conditions, the unused differential input is connected to VBB as a switching reference voltage. VBB may also rebias AC coupled inputs. When used, decouple VBB and VCC via a 0.01 mF capacitor and limit current sourcing or sinking to 0.5 mA. When not used, VBB should be left open. The 100 Series contains temperature compensation.
http://onsemi.com MARKING DIAGRAM*
20 20 1 TSSOP-20 DT SUFFIX CASE 948E xxx EP29 ALYW 1
xxx A L Y W
= MC10 or 100 = Assembly Location = Wafer Lot = Year = Work Week
*For additional information, see Application Note AND8002/D
* Maximum Frequency > 3 GHz Typical * 500 ps Typical Propagation Delays * PECL Mode Operating Range: VCC = 3.0 V to 5.5 V * NECL Mode Operating Range: VCC = 0 V * * Safety Clamp on Inputs
with VEE = -3.0 V to -5.5 V Open Input Default State with VEE = 0 V
ORDERING INFORMATION
Device MC10EP29DT MC10EP29DTR2 MC100EP29DT Package TSSOP-20 Shipping 75 Units/Rail
TSSOP-20 2500 Tape & Reel TSSOP-20 75 Units/Rail
MC100EP29DTR2 TSSOP-20 2500 Tape & Reel
(c) Semiconductor Components Industries, LLC, 2002
1
September, 2002 - Rev. 2
Publication Order Number: MC10EP29/D
MC10EP29, MC100EP29
VCC 20 R0 19 S0 18 Q0 17 Q0 16 Q1 15 Q1 14 S1 13 R1 12 VEE 11
R
S
Q Q
Q Q CLK
S
R
D
CLK
D
1 D0
2 D0
3 VBB
4 CLK0
5 CLK0
6 CLK1
7 CLK1
8 D1
9 D1
10 VCC
Warning: All VCC and VEE pins must be externally connected to Power Supply to guarantee proper operation.
Figure 1. 20-Lead Pinout (Top View) and Logic Diagram PIN DESCRIPTION
PIN D0*, D0*; D1*, D1* R0*, R1* CLK0*, CLK0* CLK1*, CLK1* S0*, S1* Q0, Q0; Q1, Q1 VBB VCC VEE FUNCTION ECL Differential Data Inputs ECL Reset Inputs ECL Differential Clock Inputs ECL Differential Clock Inputs ECL Set Inputs ECL Differential Data Outputs Reference Voltage Output Positive Supply Negative Supply Z = LOW to HIGH Transition X = Don't Care
TRUTH TABLE
R L L H L H S L L L H H D L H X X X CLK Z Z X X X Q L H L H Undef Q H L H L Undef
* Pins will default LOW when left open.
ATTRIBUTES
Characteristics Internal Input Pulldown Resistor Internal Input Pullup Resistor ESD Protection Human Body Model Machine Model Charged Device Model Value 75 kW N/A > 2 kV > 200 V > 2 kV Level 1 UL 94 V-0 @ 0.125 in 383 Devices
Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1) Flammability Rating Transistor Count Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 1. For additional information, see Application Note AND8003/D. Oxygen Index: 28 to 34
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MC10EP29, MC100EP29
MAXIMUM RATINGS (Note 2)
Symbol VCC VEE VI Iout IBB TA Tstg qJA qJC Tsol Parameter PECL Mode Power Supply NECL Mode Power Supply PECL Mode In ut Voltage Input NECL Mode Input Voltage Output Current VBB Sink/Source Operating Temperature Range Storage Temperature Range Thermal Resistance (Junction-to-Ambient) Thermal Resistance (Junction-to-Case) Wave Solder 0 LFPM 500 LFPM std bd <2 to 3 sec @ 248C 20 TSSOP 20 TSSOP 20 TSSOP Condition 1 VEE = 0 V VCC = 0 V VEE = 0 V VCC = 0 V Continuous Surge VI VCC VI VEE Condition 2 Rating 6 -6 6 -6 50 100 0.5 -40 to +85 -65 to +150 140 100 23 to 41 265 Units V V V V mA mA mA C C C/W C/W C/W C
2. Maximum Ratings are those values beyond which device damage may occur.
10EP DC CHARACTERISTICS, PECL VCC = 3.3 V, VEE = 0 V (Note 3)
-40C Symbol IEE VOH VOL VIH VIL VBB VIHCMR IIH IIL Characteristic Power Supply Current Output HIGH Voltage (Note 4) Output LOW Voltage (Note 4) Input HIGH Voltage (Single-Ended) Input LOW Voltage (Single-Ended) Output Voltage Reference Input HIGH Voltage Common Mode Range (Differential) (Note 5) Input HIGH Current Input LOW Current 0.5 Min 35 2165 1365 2090 1365 1790 2.0 1890 Typ 46 2290 1490 Max 55 2415 1615 2415 1690 1990 3.3 150 0.5 Min 37 2230 1430 2155 1460 1855 2.0 1955 25C Typ 48 2355 1555 Max 57 2480 1680 2480 1755 2055 3.3 150 0.5 Min 40 2290 1490 2215 1490 1915 2.0 2015 85C Typ 49 2415 1615 Max 60 2540 1740 2540 1815 2115 3.3 150 Unit mA mV mV mV mV mV V mA mA
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained. 3. Input and output parameters vary 1:1 with VCC. VEE can vary +0.3 V to -2.2 V. 4. All loading with 50 W to VCC-2.0 volts. 5. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal.
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MC10EP29, MC100EP29
10EP DC CHARACTERISTICS, PECL VCC = 5.0 V, VEE = 0 V (Note 6)
-40C Symbol IEE VOH VOL VIH VIL VBB VIHCMR IIH IIL Characteristic Power Supply Current Output HIGH Voltage (Note 7) Output LOW Voltage (Note 7) Input HIGH Voltage (Single-Ended) Input LOW Voltage (Single-Ended) Output Voltage Reference Input HIGH Voltage Common Mode Range (Differential) (Note 8) Input HIGH Current Input LOW Current 0.5 Min 35 3865 3065 3790 3065 3490 2.0 3590 Typ 46 3990 3190 Max 55 4115 3315 4115 3390 3690 5.0 150 0.5 Min 37 3930 3130 3855 3130 3555 2.0 3655 25C Typ 48 4055 3255 Max 57 4180 3380 4180 3455 3755 5.0 150 0.5 Min 40 3990 3190 3915 3190 3615 2.0 3715 85C Typ 49 4115 3315 Max 60 4240 3440 4240 3515 3815 5.0 150 Unit mA mV mV mV mV mV V mA mA
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained. 6. Input and output parameters vary 1:1 with VCC. VEE can vary +2.0 V to -0.5 V. 7. All loading with 50 W to VCC-2.0 volts. 8. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal.
10EP DC CHARACTERISTICS, NECL VCC = 0 V; VEE = -5.5 V to -3.0 V (Note 9)
-40C Symbol IEE VOH VOL VIH VIL VBB VIHCMR IIH IIL Characteristic Power Supply Current Output HIGH Voltage (Note 10) Output LOW Voltage (Note 10) Input HIGH Voltage (Single-Ended) Input LOW Voltage (Single-Ended) Output Voltage Reference Input HIGH Voltage Common Mode Range (Differential) (Note 11) Input HIGH Current Input LOW Current 0.5 Min 35 -1135 -1935 -1210 -1935 -1510 -1410 Typ 46 -1010 -1810 Max 55 -885 -1685 -885 -1610 -1310 0.0 150 0.5 Min 37 -1070 -1870 -1145 -1870 -1445 -1345 25C Typ 48 -945 -1745 Max 57 -820 -1620 -820 -1545 -1245 0.0 150 0.5 Min 40 -1010 -1810 -1085 -1810 -1385 -1285 85C Typ 49 -885 -1685 Max 60 -760 -1560 -760 -1485 -1185 0.0 150 Unit mA mV mV mV mV mV V mA mA
VEE+2.0
VEE+2.0
VEE+2.0
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained. 9. Input and output parameters vary 1:1 with VCC. 10. All loading with 50 W to VCC-2.0 volts. 11. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal.
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MC10EP29, MC100EP29
100EP DC CHARACTERISTICS, PECL VCC = 3.3 V, VEE = 0 V (Note 12)
-40C Symbol IEE VOH VOL VIH VIL VBB VIHCMR IIH IIL Characteristic Power Supply Current Output HIGH Voltage (Note 13) Output LOW Voltage (Note 13) Input HIGH Voltage (Single-Ended) Input LOW Voltage (Single-Ended) Output Voltage Reference Input HIGH Voltage Common Mode Range (Differential) (Note 14) Input HIGH Current Input LOW Current 0.5 Min 35 2155 1355 2075 1355 1775 2.0 1875 Typ 46 2280 1480 Max 55 2405 1605 2420 1675 1975 3.3 150 0.5 Min 37 2155 1355 2075 1355 1775 2.0 1875 25C Typ 48 2280 1480 Max 57 2405 1605 2420 1675 1975 3.3 150 0.5 Min 40 2155 1355 2075 1355 1775 2.0 1875 85C Typ 49 2280 1480 Max 60 2405 1605 2420 1675 1975 3.3 150 Unit mA mV mV mV mV mV V mA mA
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained. 12. Input and output parameters vary 1:1 with VCC. VEE can vary +0.3 V to -2.2 V. 13. All loading with 50 W to VCC-2.0 volts. 14. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal.
100EP DC CHARACTERISTICS, PECL VCC = 5.0 V, VEE = 0 V (Note 15)
-40C Symbol IEE VOH VOL VIH VIL VBB VIHCMR IIH IIL Characteristic Power Supply Current Output HIGH Voltage (Note 16) Output LOW Voltage (Note 16) Input HIGH Voltage (Single-Ended) Input LOW Voltage (Single-Ended) Output Voltage Reference Input HIGH Voltage Common Mode Range (Differential) (Note 17) Input HIGH Current Input LOW Current 0.5 Min 35 3855 3055 3775 3055 3475 2.0 3575 Typ 46 3980 3180 Max 55 4105 3305 4120 3375 3675 5.0 150 0.5 Min 37 3855 3055 3775 3055 3475 2.0 3575 25C Typ 48 3980 3180 Max 57 4105 3305 4120 3375 3675 5.0 150 0.5 Min 40 3855 3055 3775 3055 3475 2.0 3575 85C Typ 49 3980 3180 Max 60 4105 3305 4120 3375 3675 5.0 150 Unit mA mV mV mV mV mV V mA mA
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained. 15. Input and output parameters vary 1:1 with VCC. VEE can vary +2.0 V to -0.5 V. 16. All loading with 50 W to VCC-2.0 volts. 17. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal.
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MC10EP29, MC100EP29
100EP DC CHARACTERISTICS, NECL VCC = 0 V; VEE = -5.5 V to -3.0 V (Note 18)
-40C Symbol IEE VOH VOL VIH VIL VBB VIHCMR IIH IIL Characteristic Power Supply Current Output HIGH Voltage (Note 19) Output LOW Voltage (Note 19) Input HIGH Voltage (Single-Ended) Input LOW Voltage (Single-Ended) Output Voltage Reference Input HIGH Voltage Common Mode Range (Differential) (Note 20) Input HIGH Current Input LOW Current 0.5 Min 35 -1145 -1945 -1225 -1945 -1525 -1425 Typ 46 -1020 -1820 Max 55 -895 -1695 -880 -1625 -1325 0.0 150 0.5 Min 37 -1145 -1945 -1225 -1945 -1525 -1425 25C Typ 48 -1020 -1820 Max 57 -895 -1695 -880 -1625 -1325 0.0 150 0.5 Min 40 -1145 -1945 -1225 -1945 -1525 -1425 85C Typ 49 -1020 -1820 Max 60 -895 -1695 -880 -1625 -1325 0.0 150 Unit mA mV mV mV mV mV V mA mA
VEE+2.0
VEE+2.0
VEE+2.0
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained. 18. Input and output parameters vary 1:1 with VCC. 19. All loading with 50 W to VCC-2.0 volts. 20. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal.
AC CHARACTERISTICS VCC = 0 V; VEE = -3.0 V to -5.5 V or VCC = 3.0 V to 5.5 V; VEE = 0 V (Note 21)
-40C Symbol fmax tPLH, tPHL tS tH tRR/tRR2 tPW tJITTER VPP tr tf Characteristic Maximum Frequency (See Figure 2 Fmax/JITTER) Propagation Delay to Output Differential Setup Time Hold Time Set/Reset Recovery Minimum Pulse Width Set, Reset Cycle-to-Cycle Jitter (See Figure 2 Fmax/JITTER) Input Voltage Swing (Note 22) Output Rise/Fall Times (20% - 80%) Q, Q 150 100 500 300 .2 800 180 <1 1200 250 150 150 500 300 .2 800 210 <1 1200 300 150 175 500 300 .2 800 230 <1 1200 325 ps ps mV ps CLK S R 300 275 300 100 100 150 Min Typ > 3.0 380 380 400 20 20 80 450 475 500 350 300 325 100 100 150 Max Min 25C Typ > 3.0 420 400 420 20 20 80 500 500 525 400 350 375 100 100 150 Max Min 85C Typ > 3.0 470 450 470 20 20 80 550 550 575 Max Unit GHz ps
ps ps
21. Measured using a 750 mV source, 50% duty cycle clock source. All loading with 50 W to VCC-2.0 V. 22. VPP(min) is the minimum input swing for which AC parameters are guaranteed.
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MC10EP29, MC100EP29
900 800 VOUTpp (mV) 700 600 500 400 300 200 (JITTER) 100 0 9 8 7 6 5 4 3 2 1 4000 5000 JITTEROUT ps (RMS)
0
1000
2000
3000
FREQUENCY (MHz)
Figure 2. Fmax/Jitter
Q Driver Device Q 50 W 50 W
D Receiver Device D
V TT V TT = V CC - 2.0 V
Figure 3. Typical Termination for Output Driver and Device Evaluation (See Application Note AND8020 - Termination of ECL Logic Devices.)
Resource Reference of Application Notes
AN1404 AN1405 AN1406 AN1504 AN1568 AN1650 AN1672 AND8001 AND8002 AND8009 AND8020 - - - - - - - - - - - ECLinPS Circuit Performance at Non-Standard VIH Levels ECL Clock Distribution Techniques Designing with PECL (ECL at +5.0 V) Metastability and the ECLinPS Family Interfacing Between LVDS and ECL Using Wire-OR Ties in ECLinPS Designs The ECL Translator Guide Odd Number Counters Design Marking and Date Codes ECLinPS Plus Spice I/O Model Kit Termination of ECL Logic Devices
For an updated list of Application Notes, please see our website at http://onsemi.com.
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EE EE
EEEEEEEEEEEEE EEEEEEEEEEEEE
MC10EP29, MC100EP29
PACKAGE DIMENSIONS
TSSOP-20 DT SUFFIX PLASTIC TSSOP PACKAGE CASE 948E-02 ISSUE A
20X
K REF
M
0.15 (0.006) T U
S
0.10 (0.004)
TU
S
V
S
2X
L/2
20
11
B L
PIN 1 IDENT 1 10
J J1
-U-
N 0.15 (0.006) T U
S
A -V- N F
C D 0.100 (0.004) -T- SEATING
PLANE
G
H
DETAIL E
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer.
PUBLICATION ORDERING INFORMATION
Literature Fulfillment: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303-675-2175 or 800-344-3860 Toll Free USA/Canada Fax: 303-675-2176 or 800-344-3867 Toll Free USA/Canada Email: ONlit@hibbertco.com N. American Technical Support: 800-282-9855 Toll Free USA/Canada JAPAN: ON Semiconductor, Japan Customer Focus Center 2-9-1 Kamimeguro, Meguro-ku, Tokyo, Japan 153-0051 Phone: 81-3-5773-3850 Email: r14525@onsemi.com ON Semiconductor Website: http://onsemi.com For additional information, please contact your local Sales Representative.
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IIII IIII IIII
SECTION N-N 0.25 (0.010) M DETAIL E
K K1
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. ICONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE -W-. DIM A B C D F G H J J1 K K1 L M MILLIMETERS MIN MAX 6.40 6.60 4.30 4.50 --1.20 0.05 0.15 0.50 0.75 0.65 BSC 0.27 0.37 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0_ 8_ INCHES MIN MAX 0.252 0.260 0.169 0.177 --0.047 0.002 0.006 0.020 0.030 0.026 BSC 0.011 0.015 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0_ 8_
-W-
MC10EP29/D

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